1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device for defining intervals between an opening edge of the emitter of a bipolar transistor and an opening edge of the base of the bipolar transistor and between the opening edge of the emitter of the bipolar transistor and an opening edge of the collector of the bipolar transistor.
2. Description of the Related Art
In recent years, in order to achieve high speed operation and high integration by decreasing a parasitic element such as a base resistor, a micropatterned active element, such as a self-aligned bipolar transistor has been manufactured.
In a method of manufacturing a self-aligned bipolar transistor, in order to form collector, emitter, and base electrodes, at least three lithographic steps, i.e., a patterning step for an emitter extracting electrode polysilicon layer, a contact hole forming step for an emitter extracting electrode polysilicon layer, and a patterning step for a metal layer, such as an aluminum layer for forming the collector, the emitter, and the base, are required.
A method of manufacturing a self-aligned bipolar transistor including at least these three lithographic steps will be described below with reference to the accompanying drawings.
FIGS. 1A to 1F are sectional views respectively showing semiconductor structures in manufacturing steps of a conventional method for a self-aligned bipolar transistor.
FIG. 1A shows a sectional view of the semiconductor structure corresponding to a step in which an emitter extracting electrode polysilicon layer 309 has been formed by a normal method of manufacturing a selfaligned bipolar transistor.
As shown in FIG. 1A, a heavily doped n.sup.+ -type buried layer 302 is selectively formed in a p-type silicon substrate 301. An n-type epitaxial layer 304, serving as a collector region, and a heavily doped n.sup.+ -type diffusion region 302', serving as a collector extracting region, are formed in the heavily doped n.sup.+ -type buried layer 302. A p-type base region 306 is formed in a surface layer of an n-type epitaxial layer 304, and a field oxide film 305 is selectively formed as a element isolating region. A heavily doped p.sup.+ -type channel cut region 303 is formed below the field oxide film 305, serving as the element isolating region. A collector extracting electrode polysilicon layer 307 is formed on the heavily doped n.sup.+ -type diffusion region 302'. A base extracting electrode polysilicon layer 308 and an emitter extracting electrode polysilicon layer 309 are formed on the p-type base region 306. The polysilicon layers 308 and 309 are electrically isolated from each other by the oxide film 310. In addition, an n-type emitter region forming impurity, such as arsenic (As) 311, is ion-implanted in the emitter extracting electrode polysilicon layer 309 at a dose of 1.times.10.sup.16 cm.sup.-2.
As shown in FIG. IB, a photoresist layer 312 is formed on the entire surface of the resultant structure and developed into a predetermined shape by a photolithographic method, and the emitter extracting electrode polysilicon layer 309 is patterned into a predetermined shape using the photoresist layer 312 as a mask. The step which has been described above is the first lithographic step. In this case, when the emitter extracting electrode polysilicon layer 309 is patterned by a normal reactive ion etching method using, e.g., CF.sub.4 +O.sub.2 gas, the polysilicon layer 309 is side-etched to form side-etched portions 313. For this reason, the concentration of an impurity contained in the polysilicon layer 309 to form the emitter region is substantially decreased. The side-etched portion 313 having a depth of about 0.2 to 0.5 .mu.m is formed on the upper surface region of the emitter extracting electrode polysilicon layer 309.
As shown in FIG. 1C, the photoresist layer 312 is removed, and a photoresist layer 314 is formed on the entire surface of the resultant structure again. The photoresist layer 314 is developed to have a predetermined shape, and contact holes 315, respectively reaching the collector extracting electrode polysilicon layer 307 and the base extracting electrode polysilicon layer 308, are formed in the oxide film 310 using the photoresist layer 314 as a mask. The step which has been described above is the second lithographic step.
As shown in FIG. 1D, the photoresist layer 314 is removed, and the arsenic 311 serving as an emitter region forming impurity is thermally diffused in the emitter extracting electrode polysilicon layer 309 to form a heavily doped n.sup.+ -type emitter region 316 in the p-type base region 306. An aluminum layer 317 is formed on the entire surface of the resultant structure by, e.g., a sputtering method.
In FIG. 1E, a photoresist layer 318 is applied to the entire surface of the resultant structure, and the photoresist layer 318 is developed by a photographic method to have a predetermined shape. The aluminum layer 318 is patterned using the photoresist layer 317 as a mask to form collector, base, and emitter electrodes 319, 320, and 321. The step which has been described above is the third lithographic step.
As shown in FIG. 1F, the photoresist layer 318 is removed, and a self-aligned bipolar transistor is formed by a conventional manufacturing method.
As has been described above, a method of manufacturing a conventional self-aligned bipolar transistor includes the above three lithographic steps.
Referring to FIG. 1F, intervals between an emitter opening edge and an opening edge of a base electrode contact portion and between the emitter opening edge and an opening edge of a collector electrode contact portion will be described below according to a conventional method of manufacturing a self-aligned bipolar transistor having at least three lithographic steps.
As shown in FIG. 1F, in the first lithographic step, a space S1 serving as an alignment margin between an emitter opening edge and the emitter extracting electrode polysilicon layer 309 is required as a countermeasure against mask misalignment. The alignment margin S1 is set larger than a normal alignment margin by 0.5 .mu.m or more so as not to decrease an effective concentration of the impurity ion implanted in the emitter extracting electrode polysilicon layer 309 to form an emitter region.
In order to solve the above problem in which the emitter extracting electrode polysilicon layer 309 must be formed to be larger than the normal alignment margin by 0.5 .mu.m or more, the following methods are available. The emitter extracting electrode polysilicon layer 309 may be annealed prior to patterning to sufficiently activate the impurity for forming the emitter region in the polysilicon layer 309, or the impurity for forming the emitter region may be contained by, e.g., a CVD (chemical vapor deposition) method during formation of the polysilicon layer 309. In such a method, however, the emitter region cannot be micropatterned. In the above second lithographic step, when an alignment margin between the collector extracting electrode polysilicon layer 307 and the contact hole 315, and an alignment margin between the base extracting electrode polysilicon layer 308 and the contact hole 315, are taken into consideration, these alignment margins are estimated to be included beforehand in the width of the collector extracting electrode polysilicon layer 307 and the width of the base extracting electrode polysilicon layer 308, respectively. For this reason, these margins will not be taken into further consideration. In the above third lithographic step, an alignment margin S2 between an opening edge of a collector electrode contact portion and the collector electrode 319, an alignment margin between an opening edge B of a base electrode contact portion and the base electrode 320, and an alignment margin between the emitter extracting electrode 309 and the emitter electrode 321 must be assured. Assuming that intervals between the emitter electrode 321 and the base electrode and between the emitter electrode 321 and the collector electrode 319 are commonly represented by D, an interval W between an emitter opening edge A and an opening edge B of a base electrode contact portion and an alignment margin between the emitter opening edge and an opening end B of a base contact portion are calculated by the following equation: EQU W=S1+S2+S3+D
Therefore, in this step, an element cannot be micropatterned to have a width smaller than the width W. Furthermore, the alignment margin S1 must be larger than a normal alignment margin by 0.5 .mu.m or more.
For the sake of the above limitation, in a conventional method of a self-aligned bipolar transistor, even if precision of lithography is improved, the intervals W between the emitter opening edge A and the opening edge B of the collector electrode contact portion and between the emitter opening edge A and the opening edge B of the base electrode contact portion are calculated by the following equation: EQU W=S1+S2+S3+D
Therefore, the minimum intervals W are required. In addition, in order to set the impurity concentration of the emitter region 316 to a desired concentration, the alignment margin S1 must be larger than a normal alignment margin by 0.5 .mu.m or more, and the is disadvantageous in micropatterning of an element. In addition, micropatterning of an element, i.e., a decrease in area due to micropatterning of various extracting electrode polysilicon layers is required for not only improving a degree of integration of elements but reducing a parasitic element such as a base resistor due to shortening of the base extracting electrode polysilicon layer 308.